Cliff Sze
His research interests include optimization and the analysis of algorithms.
Authored Publications
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Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration
Johann Knechtel
Ozgur Sinanoglu
Ibrahim (Abe) M. Elfadel
Jens Lienig
IPSJ Trans. System LSI Design Methodology (2017)
Preview abstract
Three-dimensional (3D) integration of electronic chips has been advocated by both industry and academia
for many years. It is acknowledged as one of the most promising approaches to meet ever-increasing demands on
performance, functionality, and power consumption. Furthermore, 3D integration has been shown to be most effective
and efficient once large-scale integration is targeted for. However, a multitude of challenges has thus far obstructed
the mainstream transition from “classical 2D chips” to such large-scale 3D chips. In this paper, we survey all popular
3D integration options available and advocate that using an interposer as system-level integration backbone would
be the most practical for large-scale industrial applications and design reuse. We review major design (automation)
challenges and related promising solutions for interposer-based 3D chips in particular, among the other 3D options.
Thereby we outline (i) the need for a unified workflow, especially once full-custom design is considered, (ii) the current
design-automation solutions and future prospects for both classical (digital) and advanced (heterogeneous) interposer
stacks, (iii) the state-of-art and open challenges for testing of 3D chips, and (iv) the challenges of securing hardware in
general and the prospects for large-scale and trustworthy 3D chips in particular.
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Fast and Highly Scalable Bayesian MDP on a GPU Platform
He Zhou
Sunil P. Khatri
Jiang Hu
Frank Liu
ACM Conference on Bioinformatics, Computational Biology, and Health Informatics (ACM BCB), ACM (2017)
Preview abstract
By employing Optimal Bayesian Robust (OBR), Bayesian Markov
Decision Process (BMDP) can be a power optimization method to
solve large problems. However, due to the “curse of dimensionality”,
the data storage limitation hinders the practical application of
BMDP. To overcome this impediment, we propose a novel Improved
Compressed Sparse Row (ICSR) data structure in this paper, and developed
the implementation of BMDP solver with ICSR technique
on a heterogeneous platform with GPU. The simulation results
demonstrate that our techniques achieve about a 5× reduction in
memory utilization over using full matrix, and an average speedup
of 4.1× over using full matrix. Additionally, we present a study of
the tradeoff between the runtime and the trends of result di fference
between our ICSR techniques and using full matrix.
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