Timing channel protection for a shared memory controller

This paper proposes a new memory controller design that
enables secure sharing of main memory among mutually mistrusting
parties by eliminating memory timing channels. This
study demonstrates that shared memory controllers are vulnerable
to both side channel and covert channel attacks that
exploit memory interference as timing channels. To address
this vulnerability, we identify the sources of interference in
a conventional memory controller design, and propose a
protection scheme to eliminate the interference across security
domains through two main changes: (i) a per security
domain based queueing structure, and (ii) static allocation
of time slots in the scheduling algorithm. Multi-programmed
workloads comprised of SPEC2006 benchmarks were used
to evaluate the protection scheme. The results show that the
proposed scheme completely eliminates the timing channels
in the shared memory with small hardware and performance
overheads.

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