Liang Jia
Liang received the B.Eng. degree from Soochow University in 2008, and the M. A. Sc and Ph. D degrees from Queen’s University in 2011 and 2017, respectively. And he is currently a Sr. Engineering Manager of the Wireless Power Team and Sr. Staff Engineer at Google (2017-), leading the Wireless Charging technology development and innovation. He was a Lead Engineer for supercomputing power applications at Google Cloud (2015-2017). Before joining Google, he was a Power Design Engineer with Philips Lighting Electronics, since 2011. His main responsibility was to develop new-generation high-performance light-emitting diode (LED) drivers. His current research interests include High efficiency power conversion, wireless power transfer, magnetics design and modeling, digital control and modeling technology, etc. He has published 25+ technical papers in IEEE TRANSACTIONS and conferences and has 18 patents granted, 7 patents pending.
Liang is a Sr Member of IEEE (2018-), and he served as Session Chair in the 7th Annual IEEE Energy Conversion Congress & Exposition. He is an active reviewer of all the 5 top IEEE transactions in the Power Electronics Area, i.e. TPEL (Power Electronics), TIE (Industrial Electronics), TII (Industrial Informatics), TIA (Industrial Applications), JESTPE (Journal of Emerging and Selected Topics on Power Electronics).
Liang is also actively involved in the standardization of wireless charging technologies. He is a Co-Chair, Qi Ecosystem - Specification Work Group (SWG).
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An Isolated Multilevel Quasi-Resonant Multi-Phase Single-Stage Topology for 380 V VRM Applications
IEEE Transactions on Power Electronics (2019)
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In order to increase the efficiency of modern microprocessors power supplies used in data-centers, 380 V dc power distribution system have been attracting attention for their high efficiency and high-reliability. This paper presents an innovative single-stage approach for the 380 V voltage regulator modules (VRM) based on a quasi-resonant multilevel topology constant on-time (COT) operation. The proposed topology inherently integrates the multiphase approach, providing fast phase shedding and flat high efficiency curves even at light load conditions. This is a unique advantage, which is not possible to establish in the two stage approach, which is very important in server architectures, and where high efficiency is required even at light load conditions. The paper analyses the circuit topology and proposes a control architecture for fast transient response, including the current sharing capabilities. The digital controller has been implemented in 0.16 μm lithography together with a digital pulse width-modulation (DPWM) with a 195 ps resolution, and a 40 MS/s, 7-bit ADC. Experimental results show an efficiency of 93% for a 120 A, 380 V-1.8 V VRM power supply.
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Modeling of the cascode switching structure used in Flyback converter for achieving fast startup in the deeply dimmed phase-cut LED driver is presented in this draft. The cascode structure’s inherent instability and oscillation issue is modeled and analyzed quantitatively. Three solutions are proposed to stabilize the structure and suppress the unstable voltage oscillation. Solutions are studied using the proposed model for design robustness. And this model can be further applied to the popular new high voltage (for example 650V) cascode GaN FET technology. Experimental results of a 20W phase-cut dimmable LED driver are demonstrated to verify the proposed modeling method and solutions.
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High performance cloud computing enables many key future technologies such as artificial intelligence (AI), self-driving vehicle, big data analysis, and internet of things (IoT), using clustered CPU and GPU servers in the datacenter. To improve the power efficiency and the infrastructure flexibility, the computing industry is adopting 54VDC to power the servers in the open compute racks. In this paper, a new modeling technique for a soft-switched DC-DC converter is presented and can be used to guide optimal design in different applications, for example, 54V to point-of-load (PoL) for the new open compute rack. To improve the model accuracy and reduce the complexity, this paper proposes a reduced order linear differential equation (LDE) based modeling technique to discover 1) the tank resonance involving the output inductor; 2) output current ripple and its impact on power efficiency; 3) the proper on-time control for soft switching; 4) unique bleeding mode under the heavy load; 5) output power capability of the converter; 6) the inherent output droop of the converter for phase current sharing and 7) component tolerance analysis and impact on the performance of the converter. With the power loss estimation, design guideline is provided for a reference design and design improvement based on this new modeling technique. Using the proposed method, great accuracy can be expected in the efficiency estimation. Simulation and experimental results are provided to verify the modeling technique in a 54V-1.2V 25A DC-DC converter prototype.
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As the Internet of Things (IoT) continues to proliferate, connected and smart solutions are influencing more and more areas of our lives, as well as lighting sector. From system point of view, the additional smart features will require separate power and voltage domains from LED load, therefore, integrating an auxiliary (AUX) power supply into LED drivers is an ideal option to facilitate LED luminaire system design and reduce system cost and complexity. In this paper, a cost effective architecture based on Flyback topology is proposed for both constant current (CC) output for LED drive and constant voltage (CV) output for AUX supply. A novel nonlinear ramp based control scheme is proposed to decouple the main CC power train from the CV AUX supply and avoid LED output flickering. Small signal modeling is presented to highlight the advantages of this control scheme over conventional peak current mode control. This scheme has been implemented successfully for a 40W dimmable LED driver with a 12V 3W AUX supply.
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