Vinay Banakar
Vinay Banakar specializes in Machine Learning Systems, Distributed Systems, and Operating Systems. Vinay completed his Ph.D. from the University of Wisconsin-Madison as part of the ADvanced Systems Laboratory (ADSL). Prior to that, he completed his Masters from the University of Wisconsin-Madison and his bachelors from PES University.
Authored Publications
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OBASE: Object-Based Address-Space Engineering to Improve Memory Tiering
Kan Wu
Suli Yang
Andrea Arpaci-Dusseau
Remzi Arpaci-Dusseau
Kim Keeton
USENIX Symposium on Operating Systems Design and Implementation (OSDI '26) (2026)
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Hardware and OS mechanisms for memory tiering are widely deployed, yet datacenters still overprovision DRAM. The root cause is hotness fragmentation: allocators place objects by size rather than access pattern, so hot and cold objects become interleaved within the same pages. A single hot object marks its page as active, trapping surrounding cold data in expensive DRAM. Our analysis of Google datacenter workloads shows that up to 97% of the bytes in active pages are cold and unreclaimable. We propose address-space engineering: dynamically reorganizing virtual memory so that hot objects cluster into uniformly hot pages and cold objects into uniformly cold pages. We present OBASE, a compiler-runtime system for unmanaged languages that serves as an object-aware frontend for page-aware OS backends. OBASE tracks accesses via lightweight pointer instrumentation and migrates objects at runtime using a lock-free protocol that is safe under concurrency. By reorganizing the address space, OBASE enables unmodified backends (kswapd, TMO, TPP, Memtis) to tier memory effectively. Across ten concurrent data structures, six backends, and production traces from Meta and Twitter, OBASE improves page utilization by 2–4x and reduces memory footprint by up to 70%, with only 2–5% overhead.
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Regional Policies for Memory Tiering Systems
Hayden Coffey
Sujay Yadalam
Ashwin Poduval
Shivaram Venkataraman
Michael Swift
4th Workshop on Disruptive Memory Systems (DIMES '26) (2026)
Preview abstract
State-of-the-art memory tiering systems adapt to the access pattern of a workload over time. However, workloads may exhibit multiple unique access patterns simultaneously. As a result, behavioral assumptions governing tiering decisions may not hold across the entire address space of the program. Two pages from distinct access patterns may appear identical to the tiering policy, but require different tiering decisions.
We introduce REGENT (REGional mEmory tieriNg conTroller), a memory tiering controller that partitions a program's virtual address space into regions and runs an independent instance of a tiering policy over each one. REGENT discovers these regions automatically at runtime from observed access patterns, without application hints or kernel modification, and divides fast-tier capacity among the resulting regional policies. REGENT is a starting point for an alternative axis of tiering system design: adapting over the address space with per-region policies, rather than over time alone with one global policy. On a microbenchmark combining two simultaneous access patterns, we find that partitioning alone, with every region running the same simple frequency heuristic, is enough to match the performance of a state-of-the-art tiering policy and to exceed it under high fast-tier pressure.
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Tidying Up the Address Space
Suli Yang
Kan Wu
Remzi Arpaci-Dusseau
Andrea Arpaci-Dusseau
Kim Keeton
3rd Workshop on Disruptive Memory Systems (DIMES '25) (2025)
Preview abstract
Memory tiering in datacenters does not achieve its full potential due to hotness fragmentation---the intermingling of hot and cold objects within memory pages. This fragmentation prevents page-basedreclamation systems from distinguishing truly hot pages frompages containing mostly cold objects, fundamentally limiting memory efficiency despite highly skewed accesses. We introduce address-space engineering: dynamically reorganizing application virtual address spaces to create uniformly hot and cold regions that any page-level tiering backend can manage effectively. HADES demonstrates this frontend/backend approach through a compiler-runtime system that tracks and migrates objects based on access patterns, requiring minimal developer intervention. Evaluations across ten data structures achieve up to 70% memory reduction with 3% performance overhead, showing that address space engineering enables existing reclamation systems to reclaim memory aggressively without performance degradation.
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WiscSort: External Sorting for Byte-Addressable Storage
Kan Wu
Yuvraj Patel
Kim Keeton
Andrea Arpaci-Dusseau
Remzi Arpaci-Dusseau
Proceedings of the VLDB Endowment (2023)
Preview abstract
We present WiscSort, a new approach to high-performance concurrent sorting for existing and future byte-addressable storage (BAS) devices. WiscSort carefully reduces writes, exploits random reads by splitting keys and values during sorting, and performs interference-aware scheduling with thread pool sizing to avoid I/O bandwidth degradation. We introduce the BRAID model which encompasses the unique characteristics of BAS devices. Many state-of-the-art sorting systems do not comply with the BRAID model and deliver sub-optimal performance, whereas WiscSort demonstrates the effectiveness of complying with BRAID. We show that WiscSort is 2-7x faster than competing approaches on a standard sort benchmark. We evaluate the effectiveness of key-value separation on different key-value sizes and compare our concurrency optimizations with various other concurrency models. Finally, we emulate generic BAS devices and show how our techniques perform well with various combinations of hardware properties.
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