Byte-Aware Floating-point Operations through a UNUM Computing Unit
Abstract
Most floating-point (FP) hardware support the IEEE
754 format, which defines fixed-size data types from 16 to 128 bits.
However, a range of applications benefit from different formats,
implementing different tradeoffs. This paper proposes a Variable
Precision (VP) computing unit offering a finer granularity of high
precision FP operations. The chosen memory format is derived
from UNUM type I, where the size of a number is stored within
the representation itself. The unit implements a fully pipelined
architecture, and it supports up to 512 bits of precision for both
interval and scalar computing. The user can configure the storage
format up to 8-bit granularity, and the internal computing
precision at 64-bit granularity. The system is integrated as a
RISC-V coprocessor. Dedicated compiler support exposes the unit
through a high level programming abstraction, covering all the
operating features of UNUM type I. FPGA-based measurements
show that the latency and the computation accuracy of this
system scale linearly with the memory format length set by the
user. Compared with the MPFR software library, the proposed
unit achieves speedups between 3.5x and 18x, with comparable
accuracy.
Research Areas
