Wrapper analysis methodology updates to gain ATPG coverage, with low power driven DWC placements
Abstract
In modern System-on-Chip (SoC) architectures, hierarchical Design for Testability (DFT) heavily relies on core wrapping methodologies, such as IEEE 1500, to isolate intellectual property (IP) cores and ensure high fault coverage. While shared wrapper cells repurpose existing functional flip-flops to minimize area overhead, Dedicated Wrapper Cells (DWCs) are strictly mandated when functional registers cannot guarantee independent controllability and observability at the core boundaries. A primary structural driver for power utilization in VLSI is the presence of an Integrated Clock Gating (ICG) cell which can be even within the boundary path. When an ICG dictates the clocking of boundary registers, EDA test tools automatically instantiate DWCs to bypass the gating logic. This ensures that the shift and capture clocks remain fully deterministic during test operations, preventing coverage drops caused by unconstrained functional clock-gating conditions.
However, the insertion of DWCs introduces significant challenges during External Test (Extest) Transition Delay (TD) testing. Because Extest aims to target inter-core interconnect faults, executing at-speed TD tests requires precise launch-and-capture timing. DWCs are typically driven by a slow, dedicated test clock rather than the functional high-speed clocks. Consequently, launching and capturing at-speed transitions across IP boundaries using DWCs creates complex timing bottlenecks, frequently resulting in reduced transition fault coverage on core-to-core interconnects. Furthermore, the implementation of DWCs is highly sensitive to low-power design architectures (e.g., UPF/CPF-driven flows). The physical and logical placement of DWCs must be strictly aligned with power domain boundaries. To ensure that inter-core interconnects can still be tested via Extest when the target IP core is powered down, DWCs are often required to be placed in an "always-on" power domain, or tied to the parent's voltage island rather than the switchable core domain. Misalignment of DWC placement with respect to these power domains not only compromises the integrity of the test chain during low-power modes but also necessitates the insertion of complex isolation logic, increasing both routing congestion and power consumption.
To address this, our paper describes a novel method whereby paths containing ICG or macros (CTL segments) can be effectively targeted with Extest TD coverage without inducing any functional clock instability. Along with that, this paper presents an optimized placement approach that mitigates this by directing DWC placement in a way that significantly minimizes the overall low-power cell requirements through hierarchical-specific DWC methodologies.
However, the insertion of DWCs introduces significant challenges during External Test (Extest) Transition Delay (TD) testing. Because Extest aims to target inter-core interconnect faults, executing at-speed TD tests requires precise launch-and-capture timing. DWCs are typically driven by a slow, dedicated test clock rather than the functional high-speed clocks. Consequently, launching and capturing at-speed transitions across IP boundaries using DWCs creates complex timing bottlenecks, frequently resulting in reduced transition fault coverage on core-to-core interconnects. Furthermore, the implementation of DWCs is highly sensitive to low-power design architectures (e.g., UPF/CPF-driven flows). The physical and logical placement of DWCs must be strictly aligned with power domain boundaries. To ensure that inter-core interconnects can still be tested via Extest when the target IP core is powered down, DWCs are often required to be placed in an "always-on" power domain, or tied to the parent's voltage island rather than the switchable core domain. Misalignment of DWC placement with respect to these power domains not only compromises the integrity of the test chain during low-power modes but also necessitates the insertion of complex isolation logic, increasing both routing congestion and power consumption.
To address this, our paper describes a novel method whereby paths containing ICG or macros (CTL segments) can be effectively targeted with Extest TD coverage without inducing any functional clock instability. Along with that, this paper presents an optimized placement approach that mitigates this by directing DWC placement in a way that significantly minimizes the overall low-power cell requirements through hierarchical-specific DWC methodologies.
