VCLP DFT Dashboard for Efficient Extraction of DFT-Related Electrical Violations in Multi-Power Domain Scan Stitching

Modern System-on-Chip (SoC) designs increasingly employ multi-voltage power domain architectures as a critical power-saving technique. This approach involves partitioning the chip into distinct power domains, each operating at a specific voltage level optimized for its specific functional requirements. This strategy offers numerous benefits, including reduced dynamic and leakage power consumption, enhanced performance capabilities, and extended battery life in portable applications. However, the implementation of multi-voltage designs introduces significant challenges in Design-for-Test (DFT), particularly during scan stitching. Scan stitching, a crucial step in DFT, can inadvertently create new power domain crossings, leading to electrical violations that compromise the integrity of the test infrastructure. These violations are often intertwined with existing functional electrical issues, making the task of isolating DFT-specific problems a complex and time-consuming endeavor. Traditionally, DFT engineers rely on manual analysis and iterative debugging to segregate DFT-related electrical violations from functional violations. This process is not only manually-intensive but also prone to errors, resulting in a significant bottleneck in the DFT verification flow and delaying overall project timelines. To address this challenge, we present the Verification Compiler Low Power (VCLP) DFT dashboard, an automated solution designed to streamline the identification and categorization of DFT-specific electrical violations in multi-power domain designs.

The Verification Compiler Low Power (VCLP) DFT dashboard leverages a novel approach that automatically compares electrical violations detected post-synthesis and post-scan stitching using SNPS VCLP diff utility . By analyzing the differences between these two sets of violations, the tool accurately identifies violations introduced solely due to scan stitching and other DFT-related modifications. The dashboard provides a comprehensive HTML-based report that categorizes these violations based on DFT-specific criteria, such as violations related to Embedded Deterministic Test (EDT) crossing, test point insertion, and scan chain connectivity. This detailed categorization enables DFT engineers to quickly pinpoint the root cause of the electrical issues and implement targeted fixes. Experimental results demonstrate that the Verification Compiler Low Power (VCLP) DFT dashboard significantly improves the efficiency of DFT debugging, reduces the reliance on manual analysis, and ultimately leads to a substantial reduction in overall turnaround time for DFT verification in complex multi-power domain SoC designs.

This paper introduces a method to streamline DFT analysis by comparing Verification Compiler Low Power (VCLP) before and after scan stitching. By isolating scan-stitching-specific violations, categorizing them in DFT terms, and presenting them in a user-friendly HTML dashboard, this approach streamlines the DFT workflow and provides valuable insights, ultimately enhancing VCLP performance.