Abstract
The increasing current demands of HighPerformance Computing (HPC) accelerators – including TPUs, GPUs, and custom ASICs – are rapidly exceeding the 10,000 A threshold, presenting unprecedented challenges for traditional Lateral Power Delivery (LPD) architectures. Beyond I2R loss and transient performance, system-level optimization must harmonize competing requirements in Power Integrity (PI), Signal Integrity (SI), thermal management, and mechanical/physical design. This paper evaluates the systemic benefits and trade-offs of
transitioning from LPD to Vertical Power Delivery (VPD), identifying the fundamental physical limitations and scalability bottlenecks that render lateral solutions unsustainable as current demands escalate. Critical VPD power and PI design considerations are investigated, comparing the merits of various input voltage selections and module granularities (e.g., monolithic vs. modular designs). Furthermore, several state-of-the-art VPD hardware implementations are presented, highlighting practical challenges in thermal management, mechanical warpage, and manufacturing. Finally, future trends in VPD and emerging technologies poised to further extend the performance ceiling of high-density power delivery are discussed.