Strategic TPI Guidelines for Large-Scale SoCs

In the rapidly evolving semiconductor landscape, DFT engineers face the dual challenge of maximizing fault coverage while aggressively minimizing test time and pattern volume, a pursuit that has led to a strategic resurgence in the use of Test Point Insertion (TPI). By integrating modern TPI methodologies to break down complex logic bottlenecks, engineers can significantly reduce the data volume required for high-quality testing; however, this implementation is a complex "balancing act" against stringent Power, Performance, and Area (PPA) constraints. The introduction of these physical structures often triggers significant overheads—such as silicon area expansion, critical path timing violations, and routing congestion—meaning the "sweet spot" for test point count and type varies radically across different architectures. Ultimately, achieving an optimal tradeoff between enhanced testability and cross-domain physical design requirements remains one of the most intricate hurdles in the modern hardware implementation flow.

This paper explores the granular control offered within the Siemens EDA Tessent environment to tailor test point flows for design-specific needs. We provide a comprehensive evaluation of how specific tool variables impact the final Quality of Results (QoR). By tweaking parameters such as max_control_points_per_path, observe_block_faults, cascaded_icg_synchronization, allow_in_xbounding_region, and exclude_clock_domains, we analyze which configurations yield the best performance across diverse block architectures like increasing max_control_points_per_path helps for design with high combo depth upto a certain point without impacting STA, cascaded_icg_synchronization helps better converge in TDF with designs having multi level of ICGs, allow_in_xbounding_region is useful in designs with more X sources (TPI gets concentrated in X source regions), exclude_clock_domains can be used to exclude TPI if there is high frequency domain which is properly pipelined

The ultimate goal of this work is to establish a predictive guideline. By analyzing the design netlist upfront, users can select the most effective Tessent testability configurations without waiting for a full, time-consuming ATPG QoR analysis. Furthermore, we advocate for a hierarchical test point flow whereby testpoints are focused on more ATPG critical hierarchies rather than distributed across design, demonstrating how shifting these optimizations earlier in the design hierarchy ensures faster, more predictable QoR convergence in large-scale SoCs.

In conclusion, this paper provides a deep dive into the granular controls available within the Siemens EDA Tessent environment, demonstrating how design-specific tailoring of test point flows can yield superior Quality of Results (QoR). Through a comprehensive evaluation of key parameters provided by tessent tool and little tweaks, we analyze the performance impacts across diverse block architectures