Proactive Heterogeneous Interconnect Arbitration via ML-Aware Compiler Hinting

Modern heterogeneous Systems-on-Chip (SoCs) integrate highly diverse intellectual property (IP) blocks, including latency-sensitive CPUs, Throughput-intensive GPUs, real-time streaming display/camera engines, and massive parallel Neural Processing Units (NPUs/TPUs). Arbitrating access to a shared Network-on-Chip (NoC) and memory subsystem under such diverse traffic profiles expose a critical structural bottleneck. Traditional reactive Quality of Service (QoS) and Dynamic Voltage and Frequency Scaling (DVFS) frameworks incur substantial performance and energy penalties due to phase-locked loop (PLL) lag and transient queue saturation. This paper introduces a Compiler-Assisted Interconnect Hinting (CAIH) framework that eliminates reactive latency penalties by exploiting the deterministic nature of deep learning execution graphs. We propose a lightweight Instruction Set Architecture (ISA) extension (ICH) that allows the deep learning compiler to proactively signal upcoming memory phases, operational intensity shifts, and lookahead cycles to a centralized System QoS (SQoS) arbiter via a dedicated physical sideband channel. Experimental results extracted from cycle-accurate gem5/Garnet simulations demonstrate that our proactive framework reduces average CPU memory latency by 22%, completely eliminates display buffer underflows under heavy concurrent workloads, and achieves up to a 15% reduction in LPDDR6 memory subsystem power.