Power-Efficient Test Point Insertion via Functional Logic Reuse for Enhanced Battery Life in ASIC Designs

Complex Application-Specific Integrated Circuit (ASIC) designs frequently incorporate uncontrollable or unobservable logic, which complicates manufacturing tests and compromises device reliability. While Test Point Insertion (TPI) is a proven methodology for enhancing testability and reducing pattern counts, conventional implementations introduce significant area overhead and increased leakage power consumption. This power penalty is particularly detrimental to battery-powered electronics, where idle leakage current directly degrades longevity. This paper proposes an optimized TPI architecture that mitigates these trade-offs by reusing existing functional sequential elements instead of inserting dedicated test logic. Experimental analysis demonstrates that by minimizing additional gate counts, the proposed method effectively reduces the total leakage current. For a standard battery system, reducing the idle current through this reuse strategy significantly extends the operational lifecycle. The results indicate that the proposed solution achieves high test coverage and reduced test costs while maintaining the stringent power and area constraints required for modern mobile applications.