Optimizing PPA with ATPG QoR: A Custom Testpoints Reclustering Approach for reduced congestion and leakage with improved Test QoR
Abstract
As integrated circuit designs scale in complexity, the insertion of Design-for-Test (DFT) structures—specifically logic testpoints—becomes essential to maintain high Quality of Results (QoR) in Automatic Test Pattern Generation (ATPG). However, conventional testpoint insertion often ignores physical constraints, leading to localized routing congestion and increased leakage power that can degrade the overall Power, Performance, and Area (PPA) profile.
This paper proposes a physical-aware custom testpoint reclustering approach designed to bridge the gap between testability and physical implementation. By intelligently grouping and redistributing testpoints based on spatial proximity and netlist hierarchy, our method minimizes the routing overhead typically associated with disparate test structures. Experimental results demonstrate a significant reduction in total wirelength and congestion hotspots while simultaneously lowering leakage power through optimized cell selection and placement. Crucially, these physical gains are achieved without compromising—and in some cases improving—test coverage and pattern count. This approach provides a robust framework for achieving "physical-first" DFT, ensuring that high-fault coverage does not come at the expense of design PNR QoR.
This paper proposes a physical-aware custom testpoint reclustering approach designed to bridge the gap between testability and physical implementation. By intelligently grouping and redistributing testpoints based on spatial proximity and netlist hierarchy, our method minimizes the routing overhead typically associated with disparate test structures. Experimental results demonstrate a significant reduction in total wirelength and congestion hotspots while simultaneously lowering leakage power through optimized cell selection and placement. Crucially, these physical gains are achieved without compromising—and in some cases improving—test coverage and pattern count. This approach provides a robust framework for achieving "physical-first" DFT, ensuring that high-fault coverage does not come at the expense of design PNR QoR.
