Navigating the Cutting Edge: Strategic Verification of UFS 5.0 in Next-Gen AI SoCs
Abstract
Navigating the Cutting Edge: Strategic Verification of UFS 5.0 in Next-Gen AI SoCs
Authors: Premkumar Dhanabalan, Harsha Gollapalli, Shubham Garg, Shyam Sundar , Amitkumar Gound, Akshay R, Srinivasan
Abstract
As Artificial Intelligence (AI) workloads transition from cloud-based servers to edge devices, the demand for high-speed, low-latency storage has reached an inflection point. This paper explores the strategic verification of the emerging UFS 5.0 standard within the architecture of a next-generation flagship mobile SoC. With UFS 5.0 specifications nearing finalization, early adoption is essential to meet the storage bandwidth requirements of advanced AI processing. However, integrating a nascent protocol stack—comprising UFS5.0, UniPro 3.0 and M-PHY 6.0—presents significant challenges, including hardware immaturity and late RTL delivery evolving protocol standards & ecosystem.
The approach detailed herein leverages innovative Verification IP (VIP) topologies, a "Shift-Left" performance benchmarking strategy through verification strategies, and deep collaboration with the Synopsys VIP team. These strategies are helping to successfully mitigate risks associated with unproven IP, securing system stability and gaining confidence on protocol compliance in the pre-silicon stage thereby giving indicators for tape-out readiness.
1. Introduction: The UFS 5.0 Challenge
The integration of UFS 5.0 is a pivotal milestone for modern AI-centric hardware. The foundational IPs & subsystem transition from UFS 4.0 to 5.0 involves a fundamental overhaul of the communication stack impacting every layer-to-layer interface. A primary hurdle in this cycle was the simultaneous development of the SoC and the underlying IP standards in the protocol working groups, thereby creating an evolving ecosystem across Spec, Host Design, Device Design, VIPs and Emulation models. Traditionally, SoC verification relies on silicon-proven IP and VIPs; however, for this pioneering AI chip, verification was conducted using IPs and VIPs of similarly nascent maturity to meet the growing user demand with collaborative development over Design & DV.
Furthermore, a critical development constraint existed: the High-Speed Gear 6 (HS-G6) design updates kept evolving back and forth as the standard spec evolved, posing unstable baselines . Despite this, early feedback on UFS 5.0 protocol interoperability, stringent low-power aspects and high performance was mandatory to meet aggressive product requirements. To overcome these obstacles, the core focus remained on protocol compliance, performance benchmarking, and securing foundational UFS 4.0 functionalities across critical software use cases, such as system boot, app launch and file system.
2. Strategic VIP Topologies
Standard verification typically employs a full-stack UFS VIP topology where all three layers are active. To circumvent the lack of early PHY maturity, the verification strategy pivoted to a modular approach.
2.1 RMMI Topology and "Black-Boxing" the PHY
By adapting the Reference M-PHY Module Interface (RMMI) topology, the Physical Layer (MPHY 6.0) was "black-boxed." This abstraction allowed for:
Isolated stress-testing of the UniPro 3.0 stack.
Validation of revised L1 interface signaling prior to the availability of stable PHY RTL.
Sanitization of protocol newness before integrating in Emulation environments, where physical layers cannot be emulated.
2.2 Securing the Crypto Engine and L4 CPort
Significant micro-architectural changes in the crypto engine and the L4 CPort interface required a multi-faceted monitoring approach. A secondary VIP instance was integrated in Passive Mode in CPort topology to monitor traffic without interference. To ensure data integrity, a bespoke end-to-end crypto scoreboard was implemented utilizing Synopsys Encryption and Decryption Security VIPs, providing a robust gold model for verifying secure data transfers.
3. "Shift-Left" in Performance Verification
A critical aspect of this verification cycle was the methodology used to benchmark performance before HS-G6 RTL was available.
3.1 Clock Scaling Mode
To achieve early performance feedback, a Clock Scaling Mode was implemented within the RMMI topology. When the controller and PHY were not yet ready with G6 changes, the RMMI clock was scaled to a higher calculated frequency. This effectively allowed the UFS 4.0 infrastructure to mimic UFS 5.0 data rates.
3.2 The Math
The scaling factor was derived by back-calculating the target RMMI data rate required for HS-G6 while comparing the protocol overheads (header, trailer, and stuffing) between UFS 4.0 and UFS 5.0 with estimations. This strategy enabled an earlier start for testbench infrastructure development, allowing for the identification of micro-architectural design gaps and the estimation of bandwidth capacity months ahead of schedule.
4. Navigating Protocol Ambiguity
A vital component of the performance narrative involved addressing "grey areas" within the JEDEC standard. Early in the verification cycle, a lack of clarity was identified in the specification regarding the handling of outstanding commands in high-throughput scenarios.
In collaboration with the Synopsys VIP team, critical command pipelining enhancements were developed. These included optional configuration knobs that allowed the verification environment to:
Model diverse UFS Flash implementation behaviors observed in the industry.
Validate the SoC controller's ability to handle varying depths of outstanding commands where the standard lacked explicit definitions.
Stress-test software use cases under various "virtual" flash memory response profiles.
These enhancements were pivotal in boosting performance verification, ensuring the SoC remained robust regardless of the specific interpretation of the JEDEC standard adopted by various flash vendors.
Several MIPI level protocol issues that arose out this co-development falls in grey area of the evolving standard spec that demanded deep analysis to root-cause the issue region being design or VIP and called for realignment with key stakes on standard specifications
5. Strengthening the Testsuite
The adoption of the Synopsys Standard Testsuite VIP provided several key advantages for this high-stakes integration:
Expanded Stimulus Space: The focus shifted from basic use-case verification to protocol-intensive stress testing, which exposed integration gaps early in the design phase.
Modularity and Flexibility: Enhancements made to the testsuite ensured high configurability, allowing for "as-is" reuse across different sub-blocks.
Long-term Maintainability: The modular nature of the suite ensures that as the UFS 5.0 standard matures, the maintenance overhead for future SoC iterations is significantly reduced.
6. Conclusion
The successful integration of UFS 5.0 is paramount for unlocking the full potential of next-generation AI capabilities. This work will provide critical insights into the complexities of early technology adoption and demonstrates the necessary steps for navigating the challenges of integrating immature IP in a high-stakes product development cycle. This paper will delve deep into the challenging aspects of evolving UFS technology and the ecosystem around it and how collaboration, co-development and strong partnership with Synopsys helped to build robust verification strategies to verify complex functional, low-power and performance driven SoC.
Authors: Premkumar Dhanabalan, Harsha Gollapalli, Shubham Garg, Shyam Sundar , Amitkumar Gound, Akshay R, Srinivasan
Abstract
As Artificial Intelligence (AI) workloads transition from cloud-based servers to edge devices, the demand for high-speed, low-latency storage has reached an inflection point. This paper explores the strategic verification of the emerging UFS 5.0 standard within the architecture of a next-generation flagship mobile SoC. With UFS 5.0 specifications nearing finalization, early adoption is essential to meet the storage bandwidth requirements of advanced AI processing. However, integrating a nascent protocol stack—comprising UFS5.0, UniPro 3.0 and M-PHY 6.0—presents significant challenges, including hardware immaturity and late RTL delivery evolving protocol standards & ecosystem.
The approach detailed herein leverages innovative Verification IP (VIP) topologies, a "Shift-Left" performance benchmarking strategy through verification strategies, and deep collaboration with the Synopsys VIP team. These strategies are helping to successfully mitigate risks associated with unproven IP, securing system stability and gaining confidence on protocol compliance in the pre-silicon stage thereby giving indicators for tape-out readiness.
1. Introduction: The UFS 5.0 Challenge
The integration of UFS 5.0 is a pivotal milestone for modern AI-centric hardware. The foundational IPs & subsystem transition from UFS 4.0 to 5.0 involves a fundamental overhaul of the communication stack impacting every layer-to-layer interface. A primary hurdle in this cycle was the simultaneous development of the SoC and the underlying IP standards in the protocol working groups, thereby creating an evolving ecosystem across Spec, Host Design, Device Design, VIPs and Emulation models. Traditionally, SoC verification relies on silicon-proven IP and VIPs; however, for this pioneering AI chip, verification was conducted using IPs and VIPs of similarly nascent maturity to meet the growing user demand with collaborative development over Design & DV.
Furthermore, a critical development constraint existed: the High-Speed Gear 6 (HS-G6) design updates kept evolving back and forth as the standard spec evolved, posing unstable baselines . Despite this, early feedback on UFS 5.0 protocol interoperability, stringent low-power aspects and high performance was mandatory to meet aggressive product requirements. To overcome these obstacles, the core focus remained on protocol compliance, performance benchmarking, and securing foundational UFS 4.0 functionalities across critical software use cases, such as system boot, app launch and file system.
2. Strategic VIP Topologies
Standard verification typically employs a full-stack UFS VIP topology where all three layers are active. To circumvent the lack of early PHY maturity, the verification strategy pivoted to a modular approach.
2.1 RMMI Topology and "Black-Boxing" the PHY
By adapting the Reference M-PHY Module Interface (RMMI) topology, the Physical Layer (MPHY 6.0) was "black-boxed." This abstraction allowed for:
Isolated stress-testing of the UniPro 3.0 stack.
Validation of revised L1 interface signaling prior to the availability of stable PHY RTL.
Sanitization of protocol newness before integrating in Emulation environments, where physical layers cannot be emulated.
2.2 Securing the Crypto Engine and L4 CPort
Significant micro-architectural changes in the crypto engine and the L4 CPort interface required a multi-faceted monitoring approach. A secondary VIP instance was integrated in Passive Mode in CPort topology to monitor traffic without interference. To ensure data integrity, a bespoke end-to-end crypto scoreboard was implemented utilizing Synopsys Encryption and Decryption Security VIPs, providing a robust gold model for verifying secure data transfers.
3. "Shift-Left" in Performance Verification
A critical aspect of this verification cycle was the methodology used to benchmark performance before HS-G6 RTL was available.
3.1 Clock Scaling Mode
To achieve early performance feedback, a Clock Scaling Mode was implemented within the RMMI topology. When the controller and PHY were not yet ready with G6 changes, the RMMI clock was scaled to a higher calculated frequency. This effectively allowed the UFS 4.0 infrastructure to mimic UFS 5.0 data rates.
3.2 The Math
The scaling factor was derived by back-calculating the target RMMI data rate required for HS-G6 while comparing the protocol overheads (header, trailer, and stuffing) between UFS 4.0 and UFS 5.0 with estimations. This strategy enabled an earlier start for testbench infrastructure development, allowing for the identification of micro-architectural design gaps and the estimation of bandwidth capacity months ahead of schedule.
4. Navigating Protocol Ambiguity
A vital component of the performance narrative involved addressing "grey areas" within the JEDEC standard. Early in the verification cycle, a lack of clarity was identified in the specification regarding the handling of outstanding commands in high-throughput scenarios.
In collaboration with the Synopsys VIP team, critical command pipelining enhancements were developed. These included optional configuration knobs that allowed the verification environment to:
Model diverse UFS Flash implementation behaviors observed in the industry.
Validate the SoC controller's ability to handle varying depths of outstanding commands where the standard lacked explicit definitions.
Stress-test software use cases under various "virtual" flash memory response profiles.
These enhancements were pivotal in boosting performance verification, ensuring the SoC remained robust regardless of the specific interpretation of the JEDEC standard adopted by various flash vendors.
Several MIPI level protocol issues that arose out this co-development falls in grey area of the evolving standard spec that demanded deep analysis to root-cause the issue region being design or VIP and called for realignment with key stakes on standard specifications
5. Strengthening the Testsuite
The adoption of the Synopsys Standard Testsuite VIP provided several key advantages for this high-stakes integration:
Expanded Stimulus Space: The focus shifted from basic use-case verification to protocol-intensive stress testing, which exposed integration gaps early in the design phase.
Modularity and Flexibility: Enhancements made to the testsuite ensured high configurability, allowing for "as-is" reuse across different sub-blocks.
Long-term Maintainability: The modular nature of the suite ensures that as the UFS 5.0 standard matures, the maintenance overhead for future SoC iterations is significantly reduced.
6. Conclusion
The successful integration of UFS 5.0 is paramount for unlocking the full potential of next-generation AI capabilities. This work will provide critical insights into the complexities of early technology adoption and demonstrates the necessary steps for navigating the challenges of integrating immature IP in a high-stakes product development cycle. This paper will delve deep into the challenging aspects of evolving UFS technology and the ecosystem around it and how collaboration, co-development and strong partnership with Synopsys helped to build robust verification strategies to verify complex functional, low-power and performance driven SoC.
