Navigating the Cutting Edge: A Collaborative Approach to UFS 5.0 Pre-Silicon Maturity
Abstract
As Artificial Intelligence (AI) transforms the flagship mobile landscape, storage sub-systems must evolve into high-throughput engines to accommodate the rapid growth of Large Language Models (LLMs). The integration of UFS 5.0 is foundational to this shift, yet it introduces a complex "spec-to-silicon" risk profile where protocol ambiguities can jeopardize system responsiveness. This paper explores a robust verification strategy for a next-generation AI SoC, centered on navigating an evolving ecosystem. This details a collaborative engagement with Cadence, leveraging the unique C-System Verilog hybrid architecture of the Cadence UFS VIP to achieve pre-silicon confidence. This narrative details the technical challenges of verifying nascent HS-G6 and PAM4 features, resolving standard ambiguities, and securing robust backward compatibility for high-stakes AI use cases.
1. The Moving Target
The transition to UFS 5.0, featuring HS-G6 and PAM4 signaling, represents one of the most complex leaps in the history of the Universal Flash Storage standard. For a pioneering AI SoC, the development cycle occurred concurrently with the finalization of the JEDEC and MIPI specifications. This created a "moving target" environment where the Host Design, the Device Ecosystem, and the Verification IPs were all evolving simultaneously.
In such a high-stakes environment, relying on an in-house model implementation of the protocol is a risk. Post-silicon bugs in digital protocol layers are catastrophic, often lacking the firmware workarounds and flexibility that are usually available in analog layers. To achieve true protocol maturity, it was essential to validate the design against an industry standard model that is fundamentally different from the design by its architecture & implementation. Partnering with Cadence provided this critical platform ensuring that the SoC design was robust enough to interoperate with the diverse, evolving flash device ecosystem.
2. The Architectural Advantage: Hybrid C & System Verilog
A core highlight of this engagement was the unique structural diversity offered by the Cadence VIP. While standard environments rely heavily on SystemVerilog UVM, the Cadence architecture provided a distinct technical advantage:
Multi-Language High Fidelity: The Cadence VIP utilizes a UVM based System Verilog model with an optimized C core. This C-based core provides a different perspective on timing, synchronization, and state-machine transitions.
Structural Diversity as a Filter: Because the Cadence VIP implementation differs fundamentally from SV-only models, it acted as a high-fidelity filter. It allowed the team to distinguish between "spec-legal" behavior and "implementation-specific" behavior, which is vital when the standard is still in a state of flux. This structural difference was instrumental in catching corner-case "grey areas" in the UniPro 3.0 and M-PHY 6.0 stack.
3. Achieving Seamless Integration
Integrating a sophisticated, multi-language VIP into an existing high-speed testbench presented significant engineering challenges. To maintain velocity, a high-level VIP Abstraction Layer was engineered.
The Adapters: Different VIPs possess different configuration flavors and signaling methods. We overcame this by developing custom Adapters that encapsulated Cadence-specific APIs into a unified internal abstraction.
Agnostic Infrastructure: This abstraction allowed the team to keep the entire upper-level infrastructure, including UVM stimulus, end-to-end scoreboards & system level checks completely intact.
Technical Outcome: The result was a seamless environment where the SoC design could be cross-validated against the Cadence model with a simple compilation switch. This ensured that the testsuite developed for the SoC was truly protocol-agnostic and robust.
4. Resolving Protocol Ambiguities
The collaboration with Cadence was instrumental in resolving complex challenges where the standard specification lacked explicit clarity.
Physical Layer Nuances: The verification focused on the most demanding aspects of the new standard: HS-G6 (Gear 6), PAM4 signaling, and 1b/1b encoding.
The PHY-Adapter Interface: Specific challenges were faced in the Precoding, Equalization, and Adaptation sequences. Using the Cadence VIP helped validate the revised RMMI interface, ensuring the controller correctly handled the massive data throughput and signal integrity features of M-PHY 6.0.
Spec Alignments: When discrepancies arose between the design and the VIP, the different architectural perspective of the Cadence model helped root-cause whether the issue lay in the design logic or a specific interpretation of the evolving JEDEC/MIPI specifications. This realignment with stakeholders was essential for stabilizing the ecosystem.
5. Backward Compatibility
Beyond cutting-edge speeds, UFS 5.0 must serve as a reliable foundation for the AI software stack. The Cadence VIP was utilized to benchmark the reliability of the entire data path especially when the design underwent a complete overhaul of all protocol layers, layer-to-layer interface in order to support UFS5.0 features that structurally & logically impacted legacy paths
Legacy Robustness: The VIP was employed to validate legacy UFS 4.0 paths, ensuring that the massive overhaul required for HS-G6 did not introduce regressions in foundational layers.
Use Cases: The team verified critical AI-driven operations, including System Boot, File System integrity, and Application Launch cycles. Validating these against the Cadence device model provided the final layer of confidence that the silicon would support the aggressive performance demands of the flagship AI roadmap.
6. Conclusion
The successful integration of UFS 5.0 highlights the necessity of architectural diversity in modern SoC verification. Partnering with Cadence provided the technical depth and structural variance required to navigate an evolving protocol ecosystem. By leveraging the hybrid C & System Verilog based architecture of the Cadence VIP and employing a robust abstraction strategy, the team effectively mitigated the risks of early technology adoption.
This paper will uncover specific details of the evolving UFS protocol stack and explore the ecosystem development and associated challenges. A primary focus will remain on the verification methodologies employed and the collaborative results achieved in building the latest UFS 5.0 designs. Ultimately, this work demonstrates that achieving pre-silicon confidence in a cutting-edge AI SoC requires a collaborative approach that challenges the design against the most rigorous and diverse implementations available, setting a blueprint for high-stakes IP integrations in future technology cycles.
1. The Moving Target
The transition to UFS 5.0, featuring HS-G6 and PAM4 signaling, represents one of the most complex leaps in the history of the Universal Flash Storage standard. For a pioneering AI SoC, the development cycle occurred concurrently with the finalization of the JEDEC and MIPI specifications. This created a "moving target" environment where the Host Design, the Device Ecosystem, and the Verification IPs were all evolving simultaneously.
In such a high-stakes environment, relying on an in-house model implementation of the protocol is a risk. Post-silicon bugs in digital protocol layers are catastrophic, often lacking the firmware workarounds and flexibility that are usually available in analog layers. To achieve true protocol maturity, it was essential to validate the design against an industry standard model that is fundamentally different from the design by its architecture & implementation. Partnering with Cadence provided this critical platform ensuring that the SoC design was robust enough to interoperate with the diverse, evolving flash device ecosystem.
2. The Architectural Advantage: Hybrid C & System Verilog
A core highlight of this engagement was the unique structural diversity offered by the Cadence VIP. While standard environments rely heavily on SystemVerilog UVM, the Cadence architecture provided a distinct technical advantage:
Multi-Language High Fidelity: The Cadence VIP utilizes a UVM based System Verilog model with an optimized C core. This C-based core provides a different perspective on timing, synchronization, and state-machine transitions.
Structural Diversity as a Filter: Because the Cadence VIP implementation differs fundamentally from SV-only models, it acted as a high-fidelity filter. It allowed the team to distinguish between "spec-legal" behavior and "implementation-specific" behavior, which is vital when the standard is still in a state of flux. This structural difference was instrumental in catching corner-case "grey areas" in the UniPro 3.0 and M-PHY 6.0 stack.
3. Achieving Seamless Integration
Integrating a sophisticated, multi-language VIP into an existing high-speed testbench presented significant engineering challenges. To maintain velocity, a high-level VIP Abstraction Layer was engineered.
The Adapters: Different VIPs possess different configuration flavors and signaling methods. We overcame this by developing custom Adapters that encapsulated Cadence-specific APIs into a unified internal abstraction.
Agnostic Infrastructure: This abstraction allowed the team to keep the entire upper-level infrastructure, including UVM stimulus, end-to-end scoreboards & system level checks completely intact.
Technical Outcome: The result was a seamless environment where the SoC design could be cross-validated against the Cadence model with a simple compilation switch. This ensured that the testsuite developed for the SoC was truly protocol-agnostic and robust.
4. Resolving Protocol Ambiguities
The collaboration with Cadence was instrumental in resolving complex challenges where the standard specification lacked explicit clarity.
Physical Layer Nuances: The verification focused on the most demanding aspects of the new standard: HS-G6 (Gear 6), PAM4 signaling, and 1b/1b encoding.
The PHY-Adapter Interface: Specific challenges were faced in the Precoding, Equalization, and Adaptation sequences. Using the Cadence VIP helped validate the revised RMMI interface, ensuring the controller correctly handled the massive data throughput and signal integrity features of M-PHY 6.0.
Spec Alignments: When discrepancies arose between the design and the VIP, the different architectural perspective of the Cadence model helped root-cause whether the issue lay in the design logic or a specific interpretation of the evolving JEDEC/MIPI specifications. This realignment with stakeholders was essential for stabilizing the ecosystem.
5. Backward Compatibility
Beyond cutting-edge speeds, UFS 5.0 must serve as a reliable foundation for the AI software stack. The Cadence VIP was utilized to benchmark the reliability of the entire data path especially when the design underwent a complete overhaul of all protocol layers, layer-to-layer interface in order to support UFS5.0 features that structurally & logically impacted legacy paths
Legacy Robustness: The VIP was employed to validate legacy UFS 4.0 paths, ensuring that the massive overhaul required for HS-G6 did not introduce regressions in foundational layers.
Use Cases: The team verified critical AI-driven operations, including System Boot, File System integrity, and Application Launch cycles. Validating these against the Cadence device model provided the final layer of confidence that the silicon would support the aggressive performance demands of the flagship AI roadmap.
6. Conclusion
The successful integration of UFS 5.0 highlights the necessity of architectural diversity in modern SoC verification. Partnering with Cadence provided the technical depth and structural variance required to navigate an evolving protocol ecosystem. By leveraging the hybrid C & System Verilog based architecture of the Cadence VIP and employing a robust abstraction strategy, the team effectively mitigated the risks of early technology adoption.
This paper will uncover specific details of the evolving UFS protocol stack and explore the ecosystem development and associated challenges. A primary focus will remain on the verification methodologies employed and the collaborative results achieved in building the latest UFS 5.0 designs. Ultimately, this work demonstrates that achieving pre-silicon confidence in a cutting-edge AI SoC requires a collaborative approach that challenges the design against the most rigorous and diverse implementations available, setting a blueprint for high-stakes IP integrations in future technology cycles.
