MULTI-TIERED PHYSICAL-AWARE FORMAL ENSURING LATENCY-ROBUSTNESS IN POWER MANAGEMENT ARCHITECTURE AND DESIGN
Abstract
Multi-Tiered Physical-Aware Formal: Ensuring Latency-Robustness in Power Management Architecture and Design
This poster presentation showcases a multi-tiered verification strategy designed to account for path delays. We utilize Arch-Formal for high-level architecture modeling and Formal Property Verification (FPV) for RTL analysis. Specifically, the poster will detail how we enhanced FPV with custom FV modules to mimic signal skew and CDC uncertainties. By outlining this shift-left methodology, the poster demonstrates how to ensure architectural integrity and implementation robustness while mitigating the need for expensive physical design iterations.
This poster presentation showcases a multi-tiered verification strategy designed to account for path delays. We utilize Arch-Formal for high-level architecture modeling and Formal Property Verification (FPV) for RTL analysis. Specifically, the poster will detail how we enhanced FPV with custom FV modules to mimic signal skew and CDC uncertainties. By outlining this shift-left methodology, the poster demonstrates how to ensure architectural integrity and implementation robustness while mitigating the need for expensive physical design iterations.
