Left-Shifting Scandump DFT and RTL Validation via SimXL and Gate-Level Emulation (GLE)

Abstract— This paper explores the implementation, integration, and impact of Synopsys Simulation Acceleration (SimXL) with Gate Level Emulation (GLE) in System-on-Chip (SoC) Design Verification (DV) environments. Transitioning to simulation acceleration involves structural modifications to Device Under Test (DUT) views, memory models, and testbench clock architectures. This paper presents the critical bring-up challenges resolved during multiple SoC deployments, details the hardware domain footprints, formalizes a single-source Dual-Top Testbench Architecture, and frames optimization paradigms for acceleratable Split-Transactor Bus Trackers and DPI-C Backdoor Memory Preloading required to eliminate synchronization bottlenecks. When applied to Scandump validation, the proposed flow delivers a 90x speedup in simulation runtimes, transforming validation tasks that traditionally span 3 to 4 days down to mere hours. This enables the deep pre-silicon discovery of critical DFT and RTL bugs prior to RTL freeze, eliminating the high costs and risks associated with post-RTL freeze ECOs.