Late Breaking Results: Hierarchical ML-Framework for Rapid RDL and Bump Optimisation in GPIO-Encroached Flip-Chip SoCs

SoC designs face GPIO encroachment forcing irregular redistribution layer and bump rearrangements on upper-most BEOL metal layers. Optimising density, pitch, and power grid mesh lacks automated methods. We present a hierarchical two-stage ML framework for rapid RDL and bump encroachment modelling in GPIO-constrained flip-chip SoCs. Stage 1 employs classification and regression with sliding-window feature aggregation to predict instance-level IR drop. These predictions aggregate spatially to tile-level features that feed Stage 2, which predicts top-metal voltages for each power net. Validated on industrial sub-micron designs with 25M+ instances, achieving 20-50x acceleration with MAE ≤ 1 mV, R2 ≥ 0.995 accuracy. This enables rapid exploration of 100’s configurations, saving up to 25% cost in die area & package penalties for volume production.