IO coherency verification using PPS/perspec model
Abstract
Introduction
Modern System-on-Chips (SoCs) integrate multiple fully coherent CPU cores alongside I/O-coherent peripherals (such as PCIe endpoints) that share access to main memory. Verifying the I/O coherency of these designs presents severe challenges for verification teams, primarily due to the difficulty of manually orchestrating complex, concurrent memory accesses between diverse system agents
Challenges in I/O Coherency Verification
Complex Snoop Path Verification When an I/O coherent core accesses a snoop-able memory region, the system's coherent interconnect must correctly check if the data resides in the caches of FULL coherent cores and supply the most up-to-date data. Manually writing tests to randomly pick a mix of FULL coherent cores and I/O coherent cores to operate on the exact same snoop-able regions to aggressively exercise these snoop paths is highly inefficient and error-prone.
Orchestrating Concurrent True and False-Sharing To thoroughly stress the coherency protocol, engineers must create extremely precise concurrent scenarios, such as false-sharing with I/O, where embedded processor cores and one or more I/O devices access different byte offsets within the exact same cache lines simultaneously. This is necessary to force complex cache snoops from the I/O devices. Writing and synchronizing these scenarios manually—or combining them with true-sharing scenarios where processors and I/O devices safely pass data back and forth—is incredibly difficult to schedule without introducing unintended deadlocks or test failures
Lack of Reusable, Self-Checking Scenarios Without an automated, model-based approach, aggressively testing cache stashing, shared memory allocation, and I/O cache line invalidation (I/O deallocation) requires writing platform-specific C or SystemVerilog code. Teams lack out-of-the-box, self-checking scenarios that can predictably stress the I/O coherency protocols across virtual platforms, hardware emulation, and silicon without having to rewrite the tests from scratch
Solution: The PSS based Coherency Library
To address the severe bottlenecks of verifying I/O coherency in multi-core SoCs, the Cadence Perspec System Traffic Libraries (STL) provide a dedicated Coherency Library. This library utilizes the Portable Test and Stimulus Standard (PSS) to deliver out-of-the-box, highly configurable verification plans and test suites specifically designed for heterogeneous, cache-coherent processors and I/O devices.
Attached the abstract paper for review.
Modern System-on-Chips (SoCs) integrate multiple fully coherent CPU cores alongside I/O-coherent peripherals (such as PCIe endpoints) that share access to main memory. Verifying the I/O coherency of these designs presents severe challenges for verification teams, primarily due to the difficulty of manually orchestrating complex, concurrent memory accesses between diverse system agents
Challenges in I/O Coherency Verification
Complex Snoop Path Verification When an I/O coherent core accesses a snoop-able memory region, the system's coherent interconnect must correctly check if the data resides in the caches of FULL coherent cores and supply the most up-to-date data. Manually writing tests to randomly pick a mix of FULL coherent cores and I/O coherent cores to operate on the exact same snoop-able regions to aggressively exercise these snoop paths is highly inefficient and error-prone.
Orchestrating Concurrent True and False-Sharing To thoroughly stress the coherency protocol, engineers must create extremely precise concurrent scenarios, such as false-sharing with I/O, where embedded processor cores and one or more I/O devices access different byte offsets within the exact same cache lines simultaneously. This is necessary to force complex cache snoops from the I/O devices. Writing and synchronizing these scenarios manually—or combining them with true-sharing scenarios where processors and I/O devices safely pass data back and forth—is incredibly difficult to schedule without introducing unintended deadlocks or test failures
Lack of Reusable, Self-Checking Scenarios Without an automated, model-based approach, aggressively testing cache stashing, shared memory allocation, and I/O cache line invalidation (I/O deallocation) requires writing platform-specific C or SystemVerilog code. Teams lack out-of-the-box, self-checking scenarios that can predictably stress the I/O coherency protocols across virtual platforms, hardware emulation, and silicon without having to rewrite the tests from scratch
Solution: The PSS based Coherency Library
To address the severe bottlenecks of verifying I/O coherency in multi-core SoCs, the Cadence Perspec System Traffic Libraries (STL) provide a dedicated Coherency Library. This library utilizes the Portable Test and Stimulus Standard (PSS) to deliver out-of-the-box, highly configurable verification plans and test suites specifically designed for heterogeneous, cache-coherent processors and I/O devices.
Attached the abstract paper for review.
