Abstract
**Background**
Traditional wafer sort procedures rely on third-party "Black Box" software that utilizes "Greedy" algorithms for path generation. This approach focuses on local, step-by-step optimization, which often leads to sub-optimal total touchdowns (TD) and hidden inefficiencies. Furthermore, these systems frequently overlook mechanical edge risks, such as probe card bent pins, and lack flexibility for custom hardware constraints.
**Objectives**
This study introduces a customer-driven procedure designed to reach the mathematical minimum for touchdowns and travel distances. The goal is to replace unverified vendor logic with transparent, AI-assisted simulations that prioritize both throughput and hardware safety.
**Methodology**
The proposed framework combines Integer Linear Programming (ILP) for global touchdown optimization with the Traveling Salesman Problem (TSP) for route efficiency. Unlike traditional methods, ILP enforces complex constraints, including "Inside Probing" only, "Edge Overhang" limits, and "Max Overlapping Hits" for micro-bump protection.
**Results**
Simulations demonstrate significant improvements over industry baselines:
- Throughput: Reduced touchdowns by up to 6.1% in "Outside Probing" scenarios (163 to 153 TD) and reached the absolute mathematical limit in "Inside Probing" cases (175 to 169 TD).
- Efficiency: TSP-based routing reduced normalized travel distance by 16%.
- Risk Mitigation: Successfully minimized repeated hits on micro-bumps and protected probe card pins through flexible "Safe-Zone" adjustments.
**Conclusion**
By adopting an AI-assisted design phase, engineers can identify optimal site layouts and maintain peak throughput while proactively mitigating mechanical risks. This methodology provides a transparent, auditable framework that optimizes both test time and probe card longevity.