High-Fidelity Benchmark Replay: A Cross-Platform Methodology for Accelerating GPU Subsystem Verification
Abstract
The verification of modern GPU subsystems—encompassing high-speed interconnects, external MMUs, and security firewalls—against real-world gaming workloads poses a significant scheduling challenge. Achieving steady-state execution for benchmarks like Manhattan 3.1 or Honkai Rail in an RTL simulation environment typically requires over 20 days, creating a prohibitive bottleneck for iterative performance and power optimization.
To overcome this, we propose a hybrid methodology that leverages two distinct hardware-assisted platforms to drastically reduce runtimes. First, we utilize Hardware Emulation (Zebu/SimXL) at the IP level to execute full benchmarks in approximately one hour, during which cycle-accurate ACE activity is captured across multi-leg interfaces into time-ordered trace logs. Second, these traces are transitioned to a simulation environment where the computationally expensive GPU core is "stubbed out" and replaced by a custom UVM Replay Framework, focusing simulation resources exclusively on the auxiliary subsystem logic.
Technical focus is placed on the architecture of the UVM Replay Agent, which parses the emulation-extracted traces and drives ACE VIP sequences. A primary innovation of this framework is the preservation of Protocol Fidelity; the agent dynamically manages transaction dependencies and inter-channel timing (AW, W, AR, R, B) to ensure the replayed traffic mirrors the original hardware-level concurrency and out-of-order behavior. To ensure functional equivalence, we implement a Memory Model Scoreboard that validates data integrity across protocol converters.
To overcome this, we propose a hybrid methodology that leverages two distinct hardware-assisted platforms to drastically reduce runtimes. First, we utilize Hardware Emulation (Zebu/SimXL) at the IP level to execute full benchmarks in approximately one hour, during which cycle-accurate ACE activity is captured across multi-leg interfaces into time-ordered trace logs. Second, these traces are transitioned to a simulation environment where the computationally expensive GPU core is "stubbed out" and replaced by a custom UVM Replay Framework, focusing simulation resources exclusively on the auxiliary subsystem logic.
Technical focus is placed on the architecture of the UVM Replay Agent, which parses the emulation-extracted traces and drives ACE VIP sequences. A primary innovation of this framework is the preservation of Protocol Fidelity; the agent dynamically manages transaction dependencies and inter-channel timing (AW, W, AR, R, B) to ensure the replayed traffic mirrors the original hardware-level concurrency and out-of-order behavior. To ensure functional equivalence, we implement a Memory Model Scoreboard that validates data integrity across protocol converters.
