Hierarchical Testing in SEQ + Streaming Fabric
Abstract
The increasing complexity of System-on-Chip (SoC) designs necessitates test methodologies that balance high coverage with reduced hardware overhead. This methodology leverages SEQ (sequential compression) to addresses :
- Test Data Volume Reduction (TDVR): Minimizes the storage required on the tester
- Test Application Time Reduction (TATR): Lowers manufacturing test costs by delivering more test data through fewer pins
- High Efficiency: Enables high-compression performance with low pin-counts, a critical requirement for modern, pin-constrained hierarchical designs
Although there is a reduction of TDV and TAT seen with SEQ, it also comes with a challenge of network extraction (IJTAG), critical DRCs that are caught late in the cycle, pattern porting and other diagnosability hurdles.
In this paper, we will be demonstrating the recent updates in the tool that are done with R&D collaboration which aims to bring new innovative methodology for left shift DRC checks, fabric bandwidth utilization by core scheduling, and mitigate the above issues, thereby increasing overall usability of the tool.
- Test Data Volume Reduction (TDVR): Minimizes the storage required on the tester
- Test Application Time Reduction (TATR): Lowers manufacturing test costs by delivering more test data through fewer pins
- High Efficiency: Enables high-compression performance with low pin-counts, a critical requirement for modern, pin-constrained hierarchical designs
Although there is a reduction of TDV and TAT seen with SEQ, it also comes with a challenge of network extraction (IJTAG), critical DRCs that are caught late in the cycle, pattern porting and other diagnosability hurdles.
In this paper, we will be demonstrating the recent updates in the tool that are done with R&D collaboration which aims to bring new innovative methodology for left shift DRC checks, fabric bandwidth utilization by core scheduling, and mitigate the above issues, thereby increasing overall usability of the tool.
