Hierarchical Functional Fault Grading: A Chiplet-Based Methodology to Supplement Structural ATPG Coverage

As semiconductor designs scale in complexity, traditional structural test methodologies—such as scan-based stuck-at and transition fault modeling—increasingly fail to address critical coverage gaps. Functional fault grading (FFG) is essential for quantifying the effectiveness of functional test suites against manufacturing defects that elude structural approaches, particularly faults related to custom circuits, security modules and non-scan memories. However, implementing FFG at the System-on-Chip (SoC) level via traditional "flat" simulations is often computationally prohibitive resulting in excessive memory footprints and convergence issue and runtimes spanning several weeks, creating significant bottlenecks that delay coverage closure and increase the risk of defect escapes.This paper shares the experience with the Siemens QFX based functional fault-grading flow, using a hierarchical, chiplet-based methodology designed to resolve these inefficiencies through modular partitioning. By decomposing the SoC into manageable sub-scopes, the flow enables highly concurrent parallel fault simulation. This methodology utilizes a specialized top-level run with "black-boxed" sub-scopes to fault simulate the integration logic and interconnect paths, ensuring holistic coverage without the overhead of a flat simulation, while ensuring the consistency with flat-run results and ATPG expectations. By transforming the simulation bottleneck into a scalable, parallelized workflow, the chiplet-based approach accelerates tape-out schedules and provides a high-confidence verification path for mission-critical silicon in high-volume manufacturing.