Google’s Faster and Earlier Chip Finishing with Seamless Power Grid Enhancement Integration

Post-route chip finishing requires resolving residual physical and electrical issues prior to sign-off. Late-stage IR-drop detection is highly problematic; traditional fixes like floorplan changes or PDN redesigns trigger costly iterations and delay time-to-market. Additionally, complex DRC rules make manual or legacy PDN optimization impractical. This work introduces an automated solution integrating OASIS and LEF/DEF formats with timing-aware constraints, delivering rapid, sign-off-quality power grid (PG) enhancement directly within standard place-and-route (P&R) flows.