Glitch-Proofing Your Silicon: A Shift-Left Approach to RTL Verification
Abstract
Abstract
This paper details a "shift-left" methodology for detecting glitch-related bugs during the RTL
design verification (DV) phase. By utilizing Cadence Xcelium (XLM) Glitch, the verification
team can intercept critical timing failures—such as those affecting asynchronous resets and
clock domain crossings—earlier in the cycle. This approach reduces reliance on late-stage
Gate-Level Simulation (GLS) and minimizes the risk of costly silicon failures.
1. Introduction: The Glitch Problem
Glitches are momentary, unwanted transitions in digital signals that can lead to catastrophic
silicon failures. Traditional RTL simulations often fail to model these behaviors, leaving
detection to full-timing GLS. However, GLS is often too slow and occurs too late in the project
timeline to allow for efficient debugging.
Two primary categories of glitches pose the highest risk:
1. Asynchronous Reset Assertion: Glitches that momentarily trigger a reset, corrupting
the state of the design.
2. Invalidation of Path Specifications: Glitches that violate timing assumptions in
multi-cycle or complex combinational paths.
This paper details a "shift-left" methodology for detecting glitch-related bugs during the RTL
design verification (DV) phase. By utilizing Cadence Xcelium (XLM) Glitch, the verification
team can intercept critical timing failures—such as those affecting asynchronous resets and
clock domain crossings—earlier in the cycle. This approach reduces reliance on late-stage
Gate-Level Simulation (GLS) and minimizes the risk of costly silicon failures.
1. Introduction: The Glitch Problem
Glitches are momentary, unwanted transitions in digital signals that can lead to catastrophic
silicon failures. Traditional RTL simulations often fail to model these behaviors, leaving
detection to full-timing GLS. However, GLS is often too slow and occurs too late in the project
timeline to allow for efficient debugging.
Two primary categories of glitches pose the highest risk:
1. Asynchronous Reset Assertion: Glitches that momentarily trigger a reset, corrupting
the state of the design.
2. Invalidation of Path Specifications: Glitches that violate timing assumptions in
multi-cycle or complex combinational paths.
