Enhancements in Memory Test for Improved Diagnosability and Comprehensive Multi-Bank Test

The relentless scaling of System-on-Chip (SoC) architectures toward sub-5nm nodes has driven a shift from standard compiled memories to highly optimized custom memory designs to meet aggressive Power, Performance, and Area (PPA) targets. However, these custom layouts introduce unique physical defect mechanisms and layout-dependent coupling faults that are often invisible to industry-standard March tests. This paper proposes a novel custom testing methodology specifically engineered for multi-bank custom memory architectures in modern SoCs. By implementing a programmable, bank-aware Built-In Self-Test (BIST) architecture, the proposed solution enables concurrent multi-bank stressing to detect inter-bank crosstalk while maintaining strict power-density limits through a custom scheduling algorithm. This methodology provides a scalable framework for ensuring high reliability in performance-critical silicon environments. Industry standard memory built in self test does not cover this. This paper presents a novel custom memory testing methodology utilizing Soft Programmable Opset Logic Addition to address potential coupling-related faults during simultaneous multi-bank access in multi-port memories. While the proposed multi-bank BIST identifies the presence of inter-bank coupling, physical localization of these defects in sub-5nm nodes requires non-invasive back-side analysis. Our methodology includes a 'Diagnostic Mode' that allows the BIST to loop specific stress patterns, enabling Laser Voltage Probing (LVP) to capture high-resolution internal waveforms. This synergy between custom BIST and optical probing significantly reduces the Time-to-Yield (TTY) by pinpointing the exact physical origin of marginal delay faults.