Detecting Crosstalk induced Static Noise Defects with a Custom Test Flow
Abstract
Modern System-on-Chips (SoCs) are susceptible to asynchronous
interface failures, particularly in advanced technology nodes where
crosstalk can induce voltage glitches, leading to critical
post-silicon defects and high Return Material Authorization (RMA)
rates. This paper details the investigation of a defect in an
asynchronous interface that was undetectable by standard structural
ATPG patterns (stuck-at and transition).
Failure analysis, including silicon debug and corner-case analysis,
revealed a noise violation in the fast corner due to extreme
cross-voltage, manifesting as a glitch at an asynchronous paths. The
failure mechanism was isolated to crosstalk occurring when
simultaneous write and read operations impacted the read path with
write values. As the affected path were asynchronous, existing
Transition fault delay test patterns could not catch the defect. It is
difficult to write a functional test to control each and every node of
design and propagate the fault effect to observation point.
To ensure production-level screening, a novel, custom test generation
flow was implemented using the Tessent tool. This custom approach
involved custom netlist modifications and generating patterns with
tessent commands with specific constraints. The generated patterns
were simulated with simulate_patterns and verified with
report_failures against the original netlist, successfully capturing
the functional glitch on the silicon. This methodology demonstrates a
critical need for, and a viable solution to, developing custom test
patterns for asynchronous interface defects that elude conventional
structural test methods.
interface failures, particularly in advanced technology nodes where
crosstalk can induce voltage glitches, leading to critical
post-silicon defects and high Return Material Authorization (RMA)
rates. This paper details the investigation of a defect in an
asynchronous interface that was undetectable by standard structural
ATPG patterns (stuck-at and transition).
Failure analysis, including silicon debug and corner-case analysis,
revealed a noise violation in the fast corner due to extreme
cross-voltage, manifesting as a glitch at an asynchronous paths. The
failure mechanism was isolated to crosstalk occurring when
simultaneous write and read operations impacted the read path with
write values. As the affected path were asynchronous, existing
Transition fault delay test patterns could not catch the defect. It is
difficult to write a functional test to control each and every node of
design and propagate the fault effect to observation point.
To ensure production-level screening, a novel, custom test generation
flow was implemented using the Tessent tool. This custom approach
involved custom netlist modifications and generating patterns with
tessent commands with specific constraints. The generated patterns
were simulated with simulate_patterns and verified with
report_failures against the original netlist, successfully capturing
the functional glitch on the silicon. This methodology demonstrates a
critical need for, and a viable solution to, developing custom test
patterns for asynchronous interface defects that elude conventional
structural test methods.
