DAC: Hierarchical Functional Fault Grading with Auto-Identification of Observation Points for Enhanced DFT Coverage in Complex SoC Designs
Abstract
As semiconductor designs increase in complexity, achieving near-zero Defective Parts Per Million (DPPM) has become a critical challenge that traditional scan-based Design-for-Test (DFT) methods often difficult to meet. Conventional structural tests often leave quality gaps in custom circuits and hard-to-detect logic, leading to costly field returns (RMA). While functional verification patterns can bridge these coverage gaps, their integration is typically hindered by unoptimized stimuli, redundant simulations, and extreme memory demands that can make "flat" SoC fault grading unfeasible.
This paper presents a transformative hierarchical fault grading methodology that overcomes these bottlenecks through two core innovations: automated identification of optimal observation points and hierarchical partitioning for parallel simulation. Our approach utilizes a proprietary algorithm to automatically pinpoint internal nodes that maximize fault detection, significantly reducing the manual effort required for final coverage closure. By breaking complex SoCs into modular sub-scopes (chiplets), our framework enables parallelized fault grading that slashes RAM requirements—reducing them from over higher compute in traditional runs to standard server levels—and converts week-long simulation cycles into a predictable workflows.
Experimental results demonstrate the high scalability of this approach: where simulating just four faults at the SoC level was previously memory-prohibitive, our hierarchical method successfully processed 10,000 faults with consistent accuracy and a multi-fold reduction in total runtime. By leveraging functional test suites to detect structural defects that traditional DFT misses, this framework ensures earlier coverage closure and eliminates late-cycle engineering changes, ultimately accelerating time-to-market for high-quality, complex SoC designs.
This paper presents a transformative hierarchical fault grading methodology that overcomes these bottlenecks through two core innovations: automated identification of optimal observation points and hierarchical partitioning for parallel simulation. Our approach utilizes a proprietary algorithm to automatically pinpoint internal nodes that maximize fault detection, significantly reducing the manual effort required for final coverage closure. By breaking complex SoCs into modular sub-scopes (chiplets), our framework enables parallelized fault grading that slashes RAM requirements—reducing them from over higher compute in traditional runs to standard server levels—and converts week-long simulation cycles into a predictable workflows.
Experimental results demonstrate the high scalability of this approach: where simulating just four faults at the SoC level was previously memory-prohibitive, our hierarchical method successfully processed 10,000 faults with consistent accuracy and a multi-fold reduction in total runtime. By leveraging functional test suites to detect structural defects that traditional DFT misses, this framework ensures earlier coverage closure and eliminates late-cycle engineering changes, ultimately accelerating time-to-market for high-quality, complex SoC designs.
