DAC 26 Automating DFT Intelligence: Addressing TCPF HotSpots at Source through Design Aware Test Points in SystemRDL-to-RTL Generators
Abstract
Modern SoCs face escalating test costs due to high Test Cycles Per Fault (TCPF) caused by architectural bottlenecks like shared buses and deep decode logic. This work introduces an "Extreme Left Shift" strategy by implementing Design-Aware Test Points (DATP) directly at the RTL Generator level.
By natively integrating enhancements such as Address Parallelism and Direct APB Control, this approach bypasses generic structural constraints. Results show a 4X improvement in TCPF and pattern count for CSR-heavy designs. This methodology delivers superior ATPG Quality of Results (QoR) and significant test cost savings compared to traditional downstream EDA gate-level solutions.
By natively integrating enhancements such as Address Parallelism and Direct APB Control, this approach bypasses generic structural constraints. Results show a 4X improvement in TCPF and pattern count for CSR-heavy designs. This methodology delivers superior ATPG Quality of Results (QoR) and significant test cost savings compared to traditional downstream EDA gate-level solutions.
