Closing the DFT Loop: Correlating Testability challenges to RTL Constructs for Precision Test Point Insertion
Abstract
The "Shift-Left" strategy in Design for Testability (DFT) aims to move test insertion to the Register Transfer Level (RTL) to fix testability challenges early in the design cycle.
It reduces overall time-to-market as it is less expensive to fix testability problems in pre-synthesized design than during physical implementation.
However, traditional RTL test point insertion (TPI) often lacks the design understanding required to address coverage gaps caused by complex coding style and high level of architecture understanding of design. This paper presents a "closed-loop" methodology that utilizes Gate-level testability analysis to localize hard-to-test hierarchies, correlating them back to specific RTL constructs for precision modification.
The proposed methodology employs a closed-loop workflow beginning with fault localization to identify hierarchies contributing to pattern inflation or coverage loss during ATPG. This is followed by a comparative Gate-level and RTL test point analysis to pinpoint hard-to-test nodes. By correlating test-point results back to the source code, specific RTL constructs—such as reconvergent fanouts or complex functional blocks—are identified as the root cause of testability limitations. Finally, the workflow implements "designer-aware" test points.
It reduces overall time-to-market as it is less expensive to fix testability problems in pre-synthesized design than during physical implementation.
However, traditional RTL test point insertion (TPI) often lacks the design understanding required to address coverage gaps caused by complex coding style and high level of architecture understanding of design. This paper presents a "closed-loop" methodology that utilizes Gate-level testability analysis to localize hard-to-test hierarchies, correlating them back to specific RTL constructs for precision modification.
The proposed methodology employs a closed-loop workflow beginning with fault localization to identify hierarchies contributing to pattern inflation or coverage loss during ATPG. This is followed by a comparative Gate-level and RTL test point analysis to pinpoint hard-to-test nodes. By correlating test-point results back to the source code, specific RTL constructs—such as reconvergent fanouts or complex functional blocks—are identified as the root cause of testability limitations. Finally, the workflow implements "designer-aware" test points.
