Catching the Uncatchable: SDC, CDC, RDC & Glitch Aware RTL Simulation methodology
Abstract
This paper presents a comprehensive methodology for shifting the verification of critical timing and constraint bugs from late-stage Gate-Level Simulation (GLS) to the RTL phase. Traditionally, issues such as asynchronous glitches, Clock Domain Crossing (CDC) failures, and incorrect Static Timing Analysis (STA) constraints are only fully validated during GLS, leading to costly iterations and delayed time-to-market.
We propose a sign-off flow that integrates verification with high-performance dynamic simulation. Central to this approach is a novel random-delay X-injection technique that models physical timing uncertainty within an RTL environment, allowing for the early detection of structural hazards.
Furthermore, we introduce a path-based SDC coverage metric that transcends traditional command-based validation, ensuring that timing exceptions—including Multi-Cycle Paths (MCPs) and False Paths (FPs)—are functionally verified against the design intent.
The methodology specifically addresses the ”pessimism gap” in glitch simulation by employing window-based analysis to filter out non-critical transitions while highlighting genuine design hazards. This flow has been successfully deployed across multiple generations of production silicon projects. For the first time, complex SDC and glitch bugs were caught purely in RTL, demonstrating massive improvements in development effort and significant reductions in total simulation runtime. By providing a scalable alternative to exhaustive GLS, this methodology enables hardware teams to achieve high-confidence
We propose a sign-off flow that integrates verification with high-performance dynamic simulation. Central to this approach is a novel random-delay X-injection technique that models physical timing uncertainty within an RTL environment, allowing for the early detection of structural hazards.
Furthermore, we introduce a path-based SDC coverage metric that transcends traditional command-based validation, ensuring that timing exceptions—including Multi-Cycle Paths (MCPs) and False Paths (FPs)—are functionally verified against the design intent.
The methodology specifically addresses the ”pessimism gap” in glitch simulation by employing window-based analysis to filter out non-critical transitions while highlighting genuine design hazards. This flow has been successfully deployed across multiple generations of production silicon projects. For the first time, complex SDC and glitch bugs were caught purely in RTL, demonstrating massive improvements in development effort and significant reductions in total simulation runtime. By providing a scalable alternative to exhaustive GLS, this methodology enables hardware teams to achieve high-confidence
