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Bitwidth Reduction via Symbolic Interval Analysis for Software Model Checking

Aleksandr Zaks
Zijiang Yang
Ilya Shlyakhter
Srihari Cadambi
Malay K. Ganai
Aarti Gupta
Pranav Ashar
IEEE Trans. on CAD of Integrated Circuits and Systems, vol. 27 (2008), pp. 1513-1517

Abstract

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