Automated Static Signal Validation and Quality Control for Subsystem based SoC Designs
Abstract
Static signal validation on FSDB files is a post-simulation verification technique where waveform data, captured in a Fast Signal Database (FSDB) from tools like VCS or Xcelium, is automatically analyzed against expected behaviors. Instead of dynamic checks during the simulation, scripts and tools parse the FSDB to examine signal values within specific time windows, verifying they match predefined criteria. These criteria can range from signals holding constant values, matching expected states, clocks running at correct frequencies, the absence of glitches, or maintaining specific relationships between signals. This automated offline analysis of the static waveform database allows for efficient regression testing and thorough validation of design signal integrity against specifications, complementing traditional testbench assertions and reducing the need for extensive manual waveform review.
Power vectors are crucial test stimuli that drive a System-on-Chip (SoC) into various distinct operational power modes, from full activity to deep sleep. They are fundamental to ensuring the SoC meets its power, performance, and functional targets across all use cases. Qualifying these power vectors in complex SoCs to ensure correct power states, clock frequencies, and deactivation of debug logic is critical but traditionally relies on slow and error-prone manual waveform analysis at Power Team. This paper introduces the Power Vector Quality Control (PVQC) tool, a Python-based solution leveraging the Synopsys PyNPI waveform library. PVQC automates the validation of power vector FSDB waveforms against a user-provided checklist and reference specifications, directly within the DV environment. By automating these checks, PVQC drastically reduces manual qualification time, minimizes iterations between Design Verification and Power teams, and enables earlier bug detection, significantly improving the efficiency and reliability of power vector sign-off. The methodology is adaptable to various SoC designs and can be integrated into existing DV flows, improving overall productivity and design quality for teams using Synopsys simulation and debug solutions.
Power vectors are crucial test stimuli that drive a System-on-Chip (SoC) into various distinct operational power modes, from full activity to deep sleep. They are fundamental to ensuring the SoC meets its power, performance, and functional targets across all use cases. Qualifying these power vectors in complex SoCs to ensure correct power states, clock frequencies, and deactivation of debug logic is critical but traditionally relies on slow and error-prone manual waveform analysis at Power Team. This paper introduces the Power Vector Quality Control (PVQC) tool, a Python-based solution leveraging the Synopsys PyNPI waveform library. PVQC automates the validation of power vector FSDB waveforms against a user-provided checklist and reference specifications, directly within the DV environment. By automating these checks, PVQC drastically reduces manual qualification time, minimizes iterations between Design Verification and Power teams, and enables earlier bug detection, significantly improving the efficiency and reliability of power vector sign-off. The methodology is adaptable to various SoC designs and can be integrated into existing DV flows, improving overall productivity and design quality for teams using Synopsys simulation and debug solutions.
