AI-Assisted Test Point Insertion for Test Time Reduction
Abstract
In modern deep-submicron System-on-Chip (SoC) designs, achieving late-stage transition fault coverage (the final 2–3%) requires a disproportionately high volume of Automatic Test Pattern Generation (ATPG) patterns, creating a severe bottleneck in test time and manufacturing costs. Traditional Test Point Insertion (TPI) flows rely on generic, uniform EDA distributions and length-prone iterative ATPG regressions requiring 3 to 5 weeks to isolate structural hard-to-detect (HTD) bottlenecks.
To resolve these limitations, this paper presents a novel apparatus and methodology utilizing a Gemini CLI-accessed Artificial Intelligence Engine for automated netlist-level diagnostics and precision testpoint allocation. By parsing synthesized netlist gate structures and analyzing logic cone density, the proposed framework instantly identifies HTD architectural archetypes—such as deep sequential state machines, asynchronous clock domain crossings, and complex arbitration trees—reducing diagnostic analysis time from weeks to 5-10 minutes.
Building upon an initial targeted reallocation strategy that demonstrated a 10–15% pattern count reduction across multiple SoC sub-systems with zero coverage loss, we extend the engine with autonomous, multi-metric testpoint volume optimization. Under this enhanced paradigm, the AI engine dynamically calculates the optimal count of test points required per specific design hierarchy based on localized structural complexity. Experimental results and predictive modeling indicate that dynamic AI-driven TPI budgeting lowers overall pattern volume by over 20%, directly translating to a ~20% reduction in tester time and silicon test costs while accelerating final sign-off timelines.
To resolve these limitations, this paper presents a novel apparatus and methodology utilizing a Gemini CLI-accessed Artificial Intelligence Engine for automated netlist-level diagnostics and precision testpoint allocation. By parsing synthesized netlist gate structures and analyzing logic cone density, the proposed framework instantly identifies HTD architectural archetypes—such as deep sequential state machines, asynchronous clock domain crossings, and complex arbitration trees—reducing diagnostic analysis time from weeks to 5-10 minutes.
Building upon an initial targeted reallocation strategy that demonstrated a 10–15% pattern count reduction across multiple SoC sub-systems with zero coverage loss, we extend the engine with autonomous, multi-metric testpoint volume optimization. Under this enhanced paradigm, the AI engine dynamically calculates the optimal count of test points required per specific design hierarchy based on localized structural complexity. Experimental results and predictive modeling indicate that dynamic AI-driven TPI budgeting lowers overall pattern volume by over 20%, directly translating to a ~20% reduction in tester time and silicon test costs while accelerating final sign-off timelines.
