Accelerating DFT Efficiency via Emulation
Abstract
This presentation introduces a robust shift-left validation methodology to modernize Design for Test (DFT) pattern verification using the Veloce emulation platform. Traditional simulation workflows are often hindered by lengthy runtimes, limited test coverage due to larger iterations.
The proposed Veloce-based approach addresses these challenges by integrating DFT vectors directly into the emulation compile flow, including STIL pattern and specialized power-capture instances via Liberty and SPEF files. We detail how this flow enables real-time performance monitoring, dynamic frequency scaling, and advanced power profiling during the pre-silicon phase.
Key outcomes include the ability to identify power leakage and Electromigration and IR drop (EMIR) issues with granular precision—aided by heat-map visualization—thereby achieving up to 10,000x acceleration in feedback loops compared to conventional simulation. Ultimately, this methodology enhances verification efficiency, reduces post-silicon bring-up risks, and ensures the delivery of high-quality, reliable vectors during silicon bringup
The proposed Veloce-based approach addresses these challenges by integrating DFT vectors directly into the emulation compile flow, including STIL pattern and specialized power-capture instances via Liberty and SPEF files. We detail how this flow enables real-time performance monitoring, dynamic frequency scaling, and advanced power profiling during the pre-silicon phase.
Key outcomes include the ability to identify power leakage and Electromigration and IR drop (EMIR) issues with granular precision—aided by heat-map visualization—thereby achieving up to 10,000x acceleration in feedback loops compared to conventional simulation. Ultimately, this methodology enhances verification efficiency, reduces post-silicon bring-up risks, and ensures the delivery of high-quality, reliable vectors during silicon bringup
