A Weighted Hierarchical Approach to Testpoint Configuration driving Efficient DFT Convergence
Abstract
As System-on-Chip (SoC) complexity scales, traditional "brute force" Design-for-Test (DFT) methodologies face significant challenges in balancing high test coverage with stringent Physical Design (PD) constraints. Conventional Testpoint Insertion (TPI) often applies a uniform distribution across the floorplan, leading to pattern count inflation and timing closure bottlenecks in Place and Route (PnR). This paper proposes a granular, hierarchical TPI methodology utilizing Siemens Tessent to optimize testability in high-complexity designs.
The core of the proposed approach is a multi-pass, "no-faulting" analytical flow that identifies specific hierarchical blocks—"testability black holes"—contributing disproportionately to Automatic Test Pattern Generation (ATPG) overhead. By shifting from a monolithic distribution to an iterative, targeted refinement strategy, testpoints are strategically placed only within ATPG-critical hierarchies. This method ensures that high fault coverage is achieved without compromising the design’s physical integrity or Static Timing Analysis (STA) targets.
Experimental results demonstrate that this hierarchical targeting significantly reduces pattern counts and total test time compared to traditional TPI. Furthermore, the reduction in global testpoint density facilitates a streamlined path through PNR, delivering a superior Quality of Results (QoR) while maintaining predictive control over silicon quality.
The core of the proposed approach is a multi-pass, "no-faulting" analytical flow that identifies specific hierarchical blocks—"testability black holes"—contributing disproportionately to Automatic Test Pattern Generation (ATPG) overhead. By shifting from a monolithic distribution to an iterative, targeted refinement strategy, testpoints are strategically placed only within ATPG-critical hierarchies. This method ensures that high fault coverage is achieved without compromising the design’s physical integrity or Static Timing Analysis (STA) targets.
Experimental results demonstrate that this hierarchical targeting significantly reduces pattern counts and total test time compared to traditional TPI. Furthermore, the reduction in global testpoint density facilitates a streamlined path through PNR, delivering a superior Quality of Results (QoR) while maintaining predictive control over silicon quality.
