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Design and Characterization of a 28-nm Bulk-CMOS Cryogenic Quantum Controller Dissipating Less than 2 mW at 3 K

Trent Huang
Sayan Das
Anthony Megrant
Rami Barends
Kunal Arya
Ben Chiaro
Zijun Chen
Yu Chen
Andrew Dunsworth
Brooks Foxen
Rob Graff
Josh Mutus
Charles Neill
Amit Vainsencher
John Martinis
IEEE Journal of Solid State Circuits, vol. 54(11) (2019), pp. 3043 - 3060
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Implementation of an error corrected quantum computer is believed to require a quantum processor with on the order of a million or more physical qubits and, in order to run such a processor, a quantum control system of similar scale will be required. Such a controller will need to be integrated within the cryogenic system and in close proximity with the quantum processor in order to make such a system practical. Here, we present a prototype cryogenic CMOS quantum controller designed in a 28-nm bulk CMOS process and optimized to implement a 4-bit XY gate instruction set for transmon qubits. After introducing the transmon qubit, including a discussion of how it is controlled, design considerations are discussed, with an emphasis on error rates and scalability. The circuit design is then discussed. Cryogenic performance of the underlying technology is presented and the results of several quantum control experiments carried out using the integrated controller are described. The paper ends with a comparison to the state of the art. It has been shown that the quantum control IC achieves comparable performance with a conventional rack mount control system while dissipating less than 2mW of total AC and DC power and requiring a digital data stream of less than 500 Mb/s.

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