Automatic Vectorization in ART (Android RunTime)
Abstract
Because all modern general-purpose CPUs support small-scale SIMD instructions (typically between 64-bit and 512-bit), modern compilers are becoming progressively better at taking advantage of SIMD
instructions automatically, a translation often referred to as vectorization or SIMDization. Since the Android O release, the optimizing compiler of ART has joined the family of vectorizing compilers with the ability to translate bytecode into native SIMD code for the target Android device. This talk will discuss the general organization of the retargetable part of the vectorizer, which is capable of automatically finding and exploiting vector instructions in bytecode without committing to one of the target SIMD architectures (currently ARM NEON (advanced SIMD), x86 SSE, and MIPS SIMD
Architecture). Furthermore the talk will present particular details of deploying the vectorizing compiler on ARM platforms - its overall impact on performance, some ARM specific considerations and
optimizations - and also will give an update on Linaro ART team's SIMD-related activities.
instructions automatically, a translation often referred to as vectorization or SIMDization. Since the Android O release, the optimizing compiler of ART has joined the family of vectorizing compilers with the ability to translate bytecode into native SIMD code for the target Android device. This talk will discuss the general organization of the retargetable part of the vectorizer, which is capable of automatically finding and exploiting vector instructions in bytecode without committing to one of the target SIMD architectures (currently ARM NEON (advanced SIMD), x86 SSE, and MIPS SIMD
Architecture). Furthermore the talk will present particular details of deploying the vectorizing compiler on ARM platforms - its overall impact on performance, some ARM specific considerations and
optimizations - and also will give an update on Linaro ART team's SIMD-related activities.
Research Areas
